Linear Feedback Shift Register with VHDL.
Stream of 0's and 1's at the Output will appear to be random but it's only a pseudorandom sequence that eventually repeats.
If the outputs of the shift register are all 0's, the shift register becomes locked into its reset state but this is prevented by
the 1 MOhm resistor and the 10 uFarad capacitor. If the Output remains at logic 0 for too long, the capacitor slowly charges up.
When the Data input of the first 4015 4-bit shift register becomes a 1, the pseudorandom sequence will restart.
Adding a led (with a transistor) at the Output shown on the schematic diagram will allow you to see the pseudorandom sequence.
As shown on the prototype circuit below, a 555 IC is used as an astable to provide the clock signal so you may easily change values if you want the sequence to cycle faster or slower. Another 555 IC is used as a monostable for switch debouncing the reset pushbutton. With values choosen above, it took about 6s for the generator to restart a sequence: You may easily calculate this using the T=R*C constant (10sec here) and the fact that Vhigh Threshold (50% of 5V) is obtained at 0.6*T (6sec here).
The 8-position switch (SW1) shown on the schematic diagram below is used to select the taps.
The maximum length of 255 states (2^8 - 1) can be obtained using these taps [8,7,6,1] or [8,6,5,3] for example.
You may obtain a list of all possible taps visiting this website.